A non-volatile memory typically contains address decoders selecting appropriate row and column of the memory matrix for a given input address. Said memory matrix is composed of cells arranged in rows and columns. The address decoder and the memory matrix have to be checked during the production test of the chip to be sure it is fabricated correctly. There can be several kinds of defects on the address decoder or the memory matrix like shorts (=short circuits) between different lines, floating inputs/outputs. The goal of the production test is to check the chips and rejecting defective chips. A typical example of a non-volatile memory is an EEPROM.
The test of the electronic memory device with the address decoder can be done by several ways. The most conservative approach is to write a dedicated pattern into the memory. The pattern needs to have a unique content on each row and column. The pattern is checked by the read operation after the write operation. A typical example of such pattern is shown in the following table, which shows a memory matrix or array with 8 rows or lines and 8 columns:
columnrow76543210010000000101000000200100000300010000400001000500000100600000010700000001
The writing of a test pattern according to above-mentioned table into a non-volatile memory is a quite time consuming operation since the writing of one word into the EEPROM memory typically takes several ms time. This became to be highly critical especially for large EEPROMs. If there are e.g. 1024 rows with 2 ms write time per row, this write operation will take more than 2 s; 1024 rows correspond to an address bus width of 10 address lines: 210=1024. These 2 s are a significant portion of the test time of the chip and has a direct impact to the chip price due to a time consuming memory test.
There are several approaches which try to completely get rid off the write operations and reducing the test time due to this.
One of the approaches uses a ROM at the end of the EEPROM memory array with a unique content in each row of the ROM. The reading of such ROM allows testing the decoding of the rows. This approach has also some drawbacks. The additional area is needed for the implementation of the ROM and the capability to check the high impedance shorts is limited since the complete test is done without using high voltage HV. The so called <<high voltage>> is used for erasing/writing of an element as a byte with 8 bits or word with 16 bits of the EEPROM. In this context, the following technical terms are used in this paper:                Cell of a memory contains one bit.        The content of a row or a line contains one or more words.        The term word or words contains m cells respectively m bits for one or more words.        
The U.S. Pat. No. 5,086,413 A describes the implementation of the circuit which allows to write all odd or even rows at the time (by one write operation). This allows to check the shorts (=short circuits) in the memory array and also shorts between the neighboring outputs of the row decoder.
The patent application US 2006/018167 A1 describes a usage of a similar structure for stress test of flash memory columns. It has to be noted, that the term <<EEPROM>> is commonly used for devices with a per-word erase capability and <<flash>> for devices which only support large-block erasure.
Reference is made to FIGS. 1a and 1b showing two embodiments of an address decoder 10 with address input lines according to the state of the art. In this case, it is shown three address input lines for addressing 8 rows WL_0, WL_1, WL_2, WL_3, WL_4, WL_5, WL_6, WL_7 of the memory matrix. So the address decoder as depicted in FIGS. 1a and 1b typically uses the address inputs addr_in_0, addr_in_1, addr_in_2 for an address bus of 3 bits in this case to select one of the 8 rows or lines.
From these address inputs addr_in_0, addr_in_1, addr_in_2, there are three inverters 11 to provide three inverted addresses addr_n_0, addr_n_1, addr_n_2. Three second inverters 12 receiving the inverted addresses addr_n_0, addr_n_1, addr_n_2 provide three addresses addr_0, addr_1, addr_2 corresponding to the state of address inputs addr_in_0, addr_in_1, addr_in_2. The six lines addr_x and their inversion addr_n_x are used and combined per three through NAND gates 13 followed by third inverters 14 for selecting particular row(s) of the memory array in the first embodiment of FIG. 1a. For the second embodiment of FIG. 1b, the six lines addr_x and their inversion addr_n_x are used and combined per three through NOR gates 15 for selecting particular rows of the memory array.
It is to be noted by reference to FIGS. 1a and 1b that, if both addr_x and addr_n_x, for example with addr_0 and addr_n_0, are forced to ‘1’, this address bit will be ignored and doing so two words are selected at the same time. If this is done consecutively for all the bits a write even/odd feature can be performed. That is a problem to be checked in a production test method.